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TTTC's Electronic Broadcasting
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IEEE Test Technology Educational
Program 2017 |
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ITC 2017 - CALL FOR
TUTORIALS PARTICIPATION
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Scope |
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The Test Technology Educational Program (TTEP’17) of the TTTC is
offering 12 half-day tutorials during the weekend before the ITC
test week. This year, the TTEP tutorials will touch the most
important topics of the test scenario, problems and solutions
taught by recognized experts of the field. |
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Register for Test Week Tutorials at the ITC Registration Page
http://itctestweek.org/registe |
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October 29, 2017
(Sunday) Morning Tutorial 1:
INTERCONNECTED IEEE STANDARDS by Teresa McLaurin, Adam Cron, Artur
Jutman
There has been a continuous development trend of IEEE Test Standards addressing access to DFT resources inside evolving packaged electronics. This tutorial will address the most popular test access standards and the most salient aspects of each. These include IEEE Stds 1149.1 (package/board connection and beyond) , 1687 (instrument access through 1149.1), 1500 (core wrapping), and P1838 (3DIC test access). These standards can interact with each other and may rely on other IEEE standards to support automated construction, and design and use methodologies which will be addressed by the authors. Tutorial 2:
PRACTICES IN HIGH SPEED I/O TESTING by Salem Abdennadher,
Saghir Shaik
With advances in VLSI technology,
packaging and architecture, Systems on Chip (SoC) continue to
increase in complexity. Increasing complexity has resulted in
an unprecedented increase in design errors, manufacturing flaws and
customer returns related to High-Speed I/O (HSIO) circuits.
This tutorial presents challenges and existing techniques to meet
test complexity of HSIO and methodologies needed to achieve the
high-quality usually mandated by the critical applications such as
automotive. Both system and block level test techniques with
particular emphasis on DFT/BIST based methods and their suitability
to production level environment are presented in this tutorial.
Additionally, this tutorial includes a section on test
practices for 2.5D/3D products with IO interfaces.
Tutorial 3:
LEARNING TECHNIQUES FOR RELIABILITY MONITORING, MITIGATION
AND ADAPTATION by Mehdi Tahoori With increasing the complexity of
digital systems and the use of advanced nanoscale technology nodes,
various process and runtime variabilities threaten the correct
operation of these systems. The interdependence of these
reliability detractors and their dependencies to circuit structure
as well as running workloads makes it very hard to derive simple
deterministic models to analyze and target them. As a result,
machine learning techniques can be used to extract useful
information which can be used to effectively monitor and improve
the reliability of digital systems. The purpose of this tutorial is
to discuss and evaluate various learning schemes in order to
analyze the reliability of the system due to various runtime
failure mechanisms which originate from process and runtime
variabilities such as thermal and voltage fluctuations, device and
interconnect aging mechanisms, as well as radiation‐induced soft
errors.
Afternoon Tutorial 4:
TARGETING "ZERO DEFECT" IC QUALITY: ADVANCED CELL AWARE FAULT MODELS AND ADAPTIVE TEST by Adit Singh
Commercial applications continue to
demand ever-higher IC quality. Meanwhile, recent experience with
new fault models suggests that current structural test
methodologies can miss significant defectivity, resulting in
increasing reliance on expensive system level tests as a final
defect screen. This two-part tutorial presents a comprehensive
study of known state-of-the-art techniques directed at targeting
“Zero-Defect” IC quality. Part one focuses on new fault models,
including the cell aware methodology, for an in-depth understanding
of the actual defects in modern standard cells that are missed by
conventional stuck-at and TDF tests but detected by the new fault
models. Part two presents adaptive test methods that employ
innovative statistical techniques to further improve test
effectiveness by optimizing the tests applied to individual
parts.
Tutorial 5:
MIXED-SIGNAL DFT & BIST: TRENDS, PRINCIPLES, AND SOLUTIONS The lack of automated analog DFT
means that analog circuitry accounts for almost all failures in
automotive mixed-signal ICs. This tutorial strives to improve
this situation. We review trends in ad hoc DFT and fault
simulation, IEEE DFT standards 1149.1, .4, .6, .7, .8, .10, and
1687, as well as ISO 26262, and then review BIST techniques for
ADC/DAC, PLL, SerDes/DDR, and random analog. Seven essential
principles of practical analog BIST are presented, concluding with
specification-based structural test. Lastly, we discuss
practical DFT techniques, ranging from quicker analog defect
coverage/tolerance simulation, and DFT simplification, to
oversampling and undersampling methods that greatly improve range,
resolution, and reusability, leading to an automatable
mixed-signal DFT strategy being developed for a future IEEE
standard.
Tutorial 6: MACHINE LEARNING FOR TEST AND TEST FOR MACHINE LEARNING by Li-C. Wang Applying "machine learning" for test has been a growing field of interest in recent years. Many applications have been successfully demonstrated. In this tutorial, I will review the basic principles of applying so-called "machine learning" in selected test applications and highlights the key challenges. Results based on actual industrial settings will be shown to explain the benefits and the barriers for developing a practical learning framework. More importantly, I will explain the fundamental difference between the "machine learning” for test and the popular machine learning employed in image/speech recognition and autonomous driving. In addition, the tutorial will review the growing trends on developing machine learning based systems such as autonomous vehicles and the challenges of test for those systems. October 30, 2017 (Monday) Morning
AUTOMOTIVE RELIABILITY & TEST STRATEGIES by Riccardo Mariani, Yervant Zorian
Tutorial 8: TESTING OF TSV-BASED 2.5D- AND 3D-STACKED ICS by Krishnendu Chakrabarty Stacked ICs with vertical interconnect containing fine-pitch micro-bumps and through-silicon vias (TSVs) are a hot-topic in design and manufacturing communities. These 2.5D- and 3D-SICs hold the promise of heterogeneous integration, inter-die connections with increased performance at lower power dissipation, increased yield and decreased product cost. This tutorial presents key concepts in 3D technology, terminology, and benefits. We discuss design, test challenges and emerging solutions for 2.5D- and 3D-SICs. Covered topics include overview of 3D integration and trend-setting products such as 2.5D-FPGA, 3D-stacked memory chips, test flows and test content for 3D chips, advanced wafer probing, 3D design-for-test architectures and ongoing IEEE P1838 standardization, and 3D test cost modeling and test-flow selection. Tutorial 9: FROM DATA TO ACTIONS: APPLICATIONS OF DATA ANALYTICS IN SEMICONDUCTOR MANUFACTURING & TEST by Yiorgos Makris, Haralampos Stratigopoulos This tutorial seeks to elucidate the
utility of data analytics in semiconductor manufacturing and test.
Relevant concepts from data analytics theory will be introduced and
agglomerated with current practice, showcasing their effectiveness
on actual case studies with industrial data. A comprehensive survey
of the relevant literature will be provided, organized around four
themes: (i) Replacement of standard tests by low-cost alternatives
and/or elimination of superfluous tests based on machine learning
techniques; (ii) Adaptive test aiming at adjusting in real-time on
a wafer-by-wafer or die-to-die basis the test content, limits, and
order; (iii) Test cost reduction by exploiting wafer-level spatial
and lot-level spatiotemporal correlations; (iv) Process monitoring
for yield loss attribution, yield estimation, outlier detection,
and yield forecasting in production migration and fab
attestation.
Afternoon
Tutorial 10: MEMORY TEST & REPAIR IN FINFET ERA by Yervant Zorian
Recent growth in content delivery has
led to an explosion in the use of embedded memories. This tutorial
will present the trends and challenges of growing memory content on
chip and how to ensure detection of today’s defects upon
manufacturing and during life time, including process variation and
FinFET specific defects including 7nm technology. BIST and Repair
solutions to address debug, diagnosis, yield optimization and data
retention of failure modes will be presented. Given the tens of
thousands of embedded memory instances in today’s SOCs, this
tutorial will also cover power management constraints, functional
timing implications, test scheduling optimization, and area
minimization options.
Tutorial 11: TEST, DIAGNOSIS, AND ROOT-CAUSE IDENTIFICATION OF FAILURES FOR BOARDS AND SYSTEMS by Bill Eklow, Krishnendu
Chakrabarty
The gap between working silicon and a working board/system is becoming more significant and problematic as technology scales and complexity grows. The result of this increasing gap is failures at the board and system level that cannot be duplicated at the component level. These failures are most often referred to as “NTFs” (No Trouble Founds). The result of these NTFs can range from higher manufacturing costs and inventories to failure to get the product out of the door. This tutorial provides a detailed background on the nature of this problem and will provide DFT, test, and root-cause identification solutions at board/system level. Tutorial 12: FROM TEST TO POST-SILICON VALIDATION: CONCEPTS AND RECENT TRENDS by Arani Sinha, Sandip Ray The tutorial provides a broad overview of post-silicon bring-up, debug, and diagnosis, and discusses fundamental concepts and current practices in this area. It introduces the spectrum of validation activities, e.g., functionality, software compatibility, electrical characteristics, speed path, etc. Activities involved in validation planning along the system life cycle are covered, and various conflicts and trade-offs are discussed. The trade-offs span a spectrum of topics, including security, power management, and physical design. The tutorial will describe approaches to repurpose Design-for-Test (DfT) infrastructure for post-silicon validation, and the collaboration areas between validation and test. Instrumentation, control, and observability technologies including tracing and triggering, scan dumping, and off-chip transport will be addressed. The focus of the tutorial is on industrial adoption and practice. |
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| Additional Information | |
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Paolo Bernardi Ilia Polian |
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| Committee | |
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GENERAL CHAIR
PROGRAM CHAIR
PAST CHAIR
FINANCE CHAIR
PUBLICITY CHAIR
PLANNING CHAIR
INDUSTRIAL RELATIONS CHAIR
AUDIO/VISUAL CHAIRS
ELECTRONIC MEDIA CHAIRS
ORGANIZING LIASONS
PROGRAM COMMITTEE
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For more information, visit us on the web
at: http://ttep.tttc-events.or
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The Test Technology Educational Program 2017 is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC) |
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IEEE Computer
Society- Test Technology Technical Council
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TTTC CHAIR Chen-Huan CHIANG Alcatel-Lucent – USA Tel: +1-480-965-3749 Email: chen-huan.chiang@alcate PAST
CHAIR TTTC
1ST VICE CHAIR SECRETARY ITC
GENERAL CHAIR TEST
WEEK COORDINATOR TUTORIALS AND EDUCATION STANDARDS EUROPE MIDDLE EAST & AFRICA STANDING COMMITTEES ELECTRONIC MEDIA |
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